Cadence Takes Design and Verification IP to Intel Developer Forum

Cadence Design Systems will be demonstrating their high-speed interface and memory IP solutions, and verification IP at the 2011 Intel Developer Forum. The demonstrations will take place in the Cadence Booth #422. The Intel Developer Forum will be held September 13-15 at the Moscone Center in San Francisco, California.

Cadence Demonstrations at Intel Developer Forum

  • A high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller IP configuration implemented in a PMC-Sierra 6Gb/s SAS Tachyon protocol controller
  • Advanced low-density parity check (LDPC) error correction IP technology suitable for high-performance Flash applications such as enterprise SSD

At the Intel Developer Forum, Cadence will present design and verification IP (VIP) that enable the integration of high-speed interface and memory IP into ASICs and SoCs. Cadence will showcase design IP for DDR4, Wide I/O, NAND flash, PCI Express 3.0 and multi-gigabit Ethernet. Cadence will also highlight their VIP Catalog, which features proven verification IP for over 30 complex protocols and over 15,000 memory device configurations, including emerging standards and open support of all major simulators and use models from IP and SoC to system level.

In addition, Cadence will present an analysis of the verification challenges posed by PCI Express Gen 3 and SuperSpeed USB, and the optimal use of verification IP in SoC and system-level verification.

More info: Cadence Design Systems