2012 Design and Verification Conference Seeking Papers and Tutorials

The Design and Verification Conference (DVCon) has issued a call for paper and panel abstract submissions, and tutorial proposals. DVCon wants engineers to present their experiences, solutions and ideas. Paper proposals are due August 15, 2011, tutorial proposals are due September 13th, and panel proposals are due September 19th. DVCon will be held February 27-March 1 in San Jose, California. DVCon 2012 is sponsored by Accellera.

DVCon 2012 Paper and Panel Topics

  • Experience using ESL and/or TLM for system-level design and verification
  • Experiences deploying a verification methodology library
  • Experiences with System-on-Chip design
  • Designing and/or verifying complex ASICs and FPGAs
  • Using multiple HDLs and/or HVLs in a design cycle
  • Techniques for generating constrained-random test, or other automated stimulus generation methods
  • Synthesizing transaction-level or abstract designs from high-level languages such as SystemC, System Verilog or C++, to RTL
  • Experiences with hardware/software co-design and co-verification
  • Experiences with mixed-signal simulation
  • Verification techniques that really work (and what did not work)
  • Verification process and resource management
  • Assertion-based verification
  • Coverage-driven verification
  • Design and verification IP experiences, good and bad
  • Any topic involving the use of an HDL or HVL
  • Debug techniques for HVL testbenches and complex software-style testbenches
  • Debug techniques for SoCs with black-box and grey-box IP
  • Debug techniques for ESL and abstract models
  • Software engineering techniques for advanced testbenches focusing on efficiency for scalability
  • Experience with formal and semi-formal techniques
  • Experience with deployment of recently approved standards

DVCon 2012 Tutorial Topics

  • SystemVerilog — using SV for verification and design with SV
  • SystemC (or more generally, C/C++ based) — design and verification of systems
  • Assertion-based verification (SystemVerilog assertions, PSL, etc.)
  • Coverage-driven verification
  • Transaction Level Modeling (TLM) and ESL Design including: architectural and algorithmic exploration, interface-based design, using IP-XACT for internal and external IP integration, hardware/software trade-offs and co-verification
  • Principles of modern design verification
  • Moving from proprietary solutions to standards-based solution for design and/or verification (SystemVerilog, SystemC, PSL all provide the ability for users to move from proprietary methods to standards-based methods)

More info: DVCon