Synopsys IC Compiler-Advanced Geometry for 20nm IC Implementation

Synopsys introduced IC Compiler-Advanced Geometry, which is a new configuration of their IC Compiler physical design product. IC Compiler-Advanced Geometry is a DPT-compliant place-and-route solution that will provide designers moving to 20 nanometers with an advanced solution. Synopsys has successfully collaborated with foundry partners and major customers to validate that IC Compiler is 20nm-ready.

The current lithography approach supporting IC manufacturing reaches a theoretical limit at the 20nm node. This makes it difficult to achieve minimum resolution for silicon structures. Two possible solutions are: (1) 20nm design must either adopt a resolution that is sparser than minimum, and therefore not silicon-efficient, or (2) the design must be split into two sets of alternating structures, each more sparse than minimum but together fully utilizing available silicon resource. The latter, termed double-pattern technology, requires a place-and-route tool to accurately generate a layout where each candidate layer can be decomposed into dual alternating patterns without undue impact on performance and device area.

IC Compiler-Advanced Geometry Highlights

  • New configuration of IC Compiler physical design product
  • Targets design support for double-patterning technology (DPT)
  • Validated by foundry partners and customers for 20nm designs
  • Formulates double patterning requirements as a generalized coloring problem
  • Placement engine and Zroute technology have both been enhanced to be DPT-driven

More info: Synopsys