Apache Design Solutions Offers Low-power Webinars

Apache Design Solutions is offering a series of low-power webinars. The webcasts will cover low power methodologies, IP integration, chip-package-system solutions, RTL power analysis, SoC power integrity, analog mixed-signal power noise, full-chip ESD integrity, and IC package power. The eight online seminars will take place at 11am (PDT) in the months of July and August.

Apache Low-power Webinars Schedule

  • Ultra-Low-Power Methodology
    Tuesday, July 19, 2011, 11:00AM – 12:00PM PDT
    Meeting the power budget and reducing operational and/or stand-by power requires a methodology that establishes power as a design target during the micro-architecture and RTL design process. Apache’s analysis-driven reduction techniques allow designers to explore different power saving modes. Once RTL optimization is completed and a synthesized netlist is available, designers can run layout-based power integrity to qualify the success of RTL stage optimizations, ensuring that the voltage drop in the chip is contained.

  • IP Integration Methodology
    Thursday, July 21, 2011, 11:00AM – 12:00PM PDT
    Today’s SoC consists of several IP, developed internally or externally. To achieve a successful integration of IP into a single chip design requires a methodology that considers the power noise impact of merging sensitive analog circuitry with high-speed digital logic on the same piece of silicon. In addition, it must handle the sharing of IP information and knowledge between disparate design groups to ensure the design will work to specification and at the lowest cost.

  • PowerArtist – RTL Power Analysis, Reduction, and Debug
    Tuesday, July 26, 2011, 11:00AM – 12:00PM PDT
    A complete RTL design-for-power platform providing fully-integrated advanced analysis and automatic reduction technologies, including sequential logic, combinatorial clock gating, memory, and data path for complex IP and SoC designs. By enabling analysis, reduction, and optimization early in the design cycle, PowerArtist helps designers meet power budget requirements and increase the power efficiency of their ICs.

  • RedHawk – SoC Power Integrity and Sign-off for 28-nm Designs
    Thursday, July 28, 2011, 11:00AM – 12:00PM PDT
    RedHawk is a next-generation dynamic power integrity solution for 28-nm power sign-off, delivering capacity to handle designs with billions of transistors, while maintaining sign-off accuracy. RedHawk enables designers to explore and identify physical design weaknesses, automatically repair the source of supply noise, analyze the impact of dynamic voltage drop on timing and jitter, verify power and signal EM, and provide a model of the chip’s power delivery network for system-level analysis.

  • Totem – Analog/Mixed-Signal Power Noise and Reliability
    Tuesday, August 2, 2011, 11:00AM – 12:00PM PDT
    Totem is a full-chip, layout-based power and noise platform for analog/mixed-signal designs. Totem addresses the challenges associated with global coupling of power/ground noise, substrate noise, and package/PCB capacitive and inductive noise for memory components such as Flash and DRAM, high-speed I/Os such as HDMI and DDR, and analog circuits such as power management ICs. Integrated with existing analog design environments, Totem provides cross-probing of analysis results with industry standard circuit design tools.

  • PathFinder – Full-chip ESD Integrity and Macro-level Dynamic ESD
    Thursday, August 4, 2011, 11:00AM – 12:00PM PDT
    The industry’s first comprehensive layout-based electrostatic discharge (ESD) integrity solution provides integrated modeling, extraction, and simulation capabilities to enable automated and exhaustive analysis of the entire IC, highlighting areas of weaknesses that can be susceptible to ESD induced failure. PathFinder also delivers innovative transistor-level dynamic ESD capabilities for validation of I/Os, analog, and mixed-signal designs.

  • Chip-Package-System (CPS) Convergence Solution
    Tuesday, August 9, 2011, 11:00AM – 12:00PM PDT
    A complete Chip-Package-System co-design/co-analysis solution addressing system-level power integrity, SSO, thermal, and EMI challenges. Apache’s Sentinel combines the chip’s core switching power delivery network, I/O sub-system, and IC package/PCB modeling and analysis in a single environment for accurate CPS convergence, from early stage prototyping to sign-off.

  • Sentinel-PSI – IC-Package Power and Signal Integrity Solution
    Thursday, August 11, 2011, 11:00AM – 12:00PM PDT
    This is a 3D full-wave electromagnetic solver for power and signal integrity analysis of IC package and PCBs, with the ability to perform DC (static), AC (frequency domain), and transient (dynamic) simulations from a single environment. Based on the fast finite element method (FFEM), Sentinel-PSI provides the accuracy of a conventional full-wave tool, with the unparalleled capacity to handle an entire package or board design. Sentinel-PSI is seamlessly connected to other Apache products in system-level analysis, and is linked with Sentinel-SSO to perform system-level I/O-SSO simulations.

More info: Apache Design Solutions