Sigrity SystemSI Signal Integrity Analysis Solutions

Sigrity launched their SystemSI family of signal integrity analysis solutions. SystemSI is a platform for end-to-end simulations of high-speed signal interfaces. SystemSI – Parallel Bus Analysis is available on Windows and Linux platforms with annual prices starting at $26,500. A Via Wizard for pre-layout studies, using 3D FEM techniques, starts at $8,000 per year. SystemSI – Serial Link Analysis is priced at $26,500 annually.

Sigrity SystemSI Chip-to-Chip Analysis

  • Comprehensive environment for end-to-end simulations of high-speed signal interfaces
  • Includes a block-based editor, support for standard modeling formats, automated model connections and highly accurate simulation
  • Realistic assessment of actual system behavior
  • Can be used at the pre-layout stage, post-layout stage, or anywhere in-between
  • SystemSI is available in two configurations: SystemSI – Serial Link Analysis, and SystemSI – Parallel Bus Analysis
  • SystemSI – Serial Link Analysis can fully analyze high-speed SerDes designs
  • SystemSI – Parallel Bus Analysis supports high-speed bus interfaces like DDRx (Dual Data Rate) memory interfaces
  • SystemSI – Parallel Bus Analysis enables engineers to quickly and comprehensively analyze timing margins for DDRx memory interfaces
  • SystemSI – Parallel Bus Analysis considers multiple effects concurrently, including dielectric/conductor loss, reflections, crosstalk, inter-symbol interference (ISI) and simultaneous switching noise (SSN)
  • Includes an intuitive block-based editor
  • TLine Editor and Via Wizard are available to facilitate creation of early approximations of system behavior
  • Interconnect models can come from a range of sources including supplier specifications, measured data and models extracted using tools
  • Model connections are automated with Sigrity’s open Model Connection Protocol (MCP) format
  • Sigrity’s Broadband SPICE improves S-parameter models that may have problems and improves the accuracy and efficiency of circuit simulation
  • Device IO modeling is supported in multiple formats, including SPICE sub-circuits, traditional IBIS format, and power-aware IBIS behavioral format

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