Synopsys 28nm Design Solutions for TSMC Reference Flow 12.0
Synopsys introduced 28nm design solutions that integrate manufacturing compliance and system-level prototyping with TSMC Reference Flow 12.0. The extended Reference Flow 12.0 reduces time-to-market and speeds time-to-volume using TSMC’s 28-nm process technology. The design enablement solution features virtual prototyping and high-level synthesis linked to TSMC’s advanced processes, expanded manufacturing compliance capabilities and full support of TSMC’s latest 28-nm design rules and models within Synopsys’ Galaxy Implementation Platform.
Synopsys Support for TSMC Reference Flow 12.0 Highlights
- Virtual Prototyping and DesignWare System-Level Library for SoC virtual prototyping and power/performance analysis
- Synphony C Compiler high-level synthesis feeding into DesignCompiler Ultra
- DesignWare IP and Verification IP for the ARM AMBA interconnect provides infrastructure and fabric components for AMBA 2.0 and AMBA 3 AXI3
- Automated assembly of the IP using coreAssembler tool
- CustomSim and HSPICE circuit simulation with TSMC 28-nm model support
- VCS with MVSIM voltage-aware simulation
- MVRC low power static checking
- SoC ESL verification using VCS with UVM 1.0
- IC Compiler place and route, including Zroute technology and dummy via insertion
- IC Validator DRC/LVS In-Design physical verification and sign-off
- DC Ultra and Design Compiler Graphical RTL synthesis including Topographical technology and congestion optimization
- DesignWare Library datapath IP
- Power Compiler power optimization and multi-voltage power management
- Formality equivalence checking
- DFTMAX compression for test cost reduction
- TetraMAX automatic test pattern generation (ATPG)
- PrimeTime static timing analysis including advanced stage-based OCV
- StarRC parasitic extraction with feature-scale VCMP, eDRAM tall contact, via-etch and trench contact modeling support
- PrimeYield LCC for automatic lithography-hotspot and pattern-match detection and fixing, and TSMC unified LPC format support
- Parasitic extraction, timing, IR-drop analysis
- Yield Explorer for physical pattern-aware, design-centric volume diagnosis isolates and prioritizes the dominant systematic failures among the scan diagnostics results
- Integration of systematic defect simulation data into yield analysis to quickly capture process marginality impacts on scan failures
More info: Synopsys
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