Silicon Frontline H3D Hierarchical 3D Extractor

Silicon Frontline Technology introduced their H3D hierarchical 3D extractor for post-layout verification. H3D eliminates post-layout verification bottlenecks. The tool does this by providing an accurate extractor that runs with sub-linear performance and delivers a hierarchical output that enables post-layout simulation speed up. H3D will start shipping in early Q3.

Silicon Frontline H3D Features

  • Industry’s first commercial hierarchical 3D extractor for post-layout verification
  • Hierarchical parasitic extraction
  • Hierarchical netlisting
  • Unlimited capacity (due to its hierarchical extraction and parallelization)
  • Field-solver accuracy
  • Works with design flows from the major EDA vendors
  • Extraction performance is sub-linear — as design size grows extraction performance improves
  • By providing a hierarchical output netlist, post-layout simulation performance becomes sub-linear when using hierarchical simulators
  • Enables post-layout simulation speed up
  • Ideal for array-based and repetitive design structures (including memories, FPGAs, and image sensors)
  • Performance improvements from 20-120x when compared to flat extraction
  • Built on a Hierarchical Random Walk Algorithm
  • Ability to specify the accuracy required on a net by net or block by block basis
  • Hierarchical output supports R, C, distributed RC and RCCc

More info: Silicon Frontline Technology