Cadence Allegro v16.5 PCB and IC Tool

Cadence Design Systems announced version 16.5 of their Allegro PCB and IC packaging technology. Allegro v16.5 features advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, improved co-design, and flexible team-design enablement. The new features and capabilities improve the path to co-design and analysis between engineers involved in Silicon, SoC, and System Realization. Cadence Allegro 16.5 will be available in late May. Allegro 16.5 technology will also be available through product configuration with on-demand features for specific design tasks.

Cadence Allegro v16.5 Highlights

  • Higher functional density with a constraint-driven flow for embedded components
  • Faster timing closure with new PCB interconnect design planning technology
  • Concurrent team design authoring capability reduces physical prototype iterations
  • More efficient low-power design with integrated power delivery network analysis
  • A compliant and faster implementation path with package-board-aware DDR3 SoC IP methodology kit
  • Smoother collaboration among global teams with new SiP distributed co-design
  • Flexibility through base plus options configurations — on-demand features for specific design tasks
  • Enables more predictable and efficient design flows
  • Direct bi-directional integration with flows from the Cadence Encounter Digital Implementation System and Virtuoso

More info: Cadence Design Systems