Tanner EDA HiPer Silicon v15.11

Tanner EDA rolled out version 15.11 of HiPer Silicon design suite. HiPer Silicon offers engineers a complete analog design flow from schematic capture, circuit simulation, and waveform probing to physical layout and verification. New features in HiPer Silicon v15.11 includes S-Edit additions, T-Spice performance improvements, W-Edit enhancements, L-Edit productivity gains, HiPer DevGen additions, and HiPer Verify enhancements.

Tanner HiPer Silicon v15.11 Features

S-Edit

  • Import Spice and Verilog added two new options (Parse Connectivity and Preserve Text)
  • Enhanced Connectivity views can be viewed and edited in SPICE format
  • Enhanced access control of designs allow better team collaboration
  • Corner Simulation Setup to easily simulate across process corners, temperatures, etc.

W-Edit

  • Units can be specified in calc and trace define commands
  • New Histogram chart type
  • Results of .MEASURE commands in a Monte Carlo simulation are automatically plotted on a histogram upon completion of the simulation
  • New eye diagrams chart type

T-Spice

  • Performance is improved in cases where large amounts of text are written to the output window
  • Inline comments may now begin with an asterisk (*) as well as the previously supported dollar sign ($)
  • Support for G element VCR voltage-controlled resistor
  • New option monteinfo for Monte Carlo analysis
  • 20% improvement Transient Simulation Performance (DC Convergence) due to new compiler and solver
  • Update of Verilog-A, SimKit, and BSIM4 SOI models

L-Edit

  • Object Snapping is now able to snap to the edge of wires
  • Paste to cursor of instances now places the cursor at the origin of the instance rather than the center of the instance
  • UPI functions added for layer palette
  • Wire drawing productivity enhancements greatly improve routing productivity
  • Object snapping to intersections

HiPer DevGen

  • Resistor generator has the ability to create resistor arrays
  • SDL Router is able to recognize resistors in a netlist that have the same L and W and combine them into a single resistor array

HiPer Verify

  • Major performance improvements for rules using Extent
  • Support for Size – Bevel option

More info: Tanner EDA