Cadence CDNLive! EMEA User Conference 2011

Cadence Design Systems will hold their CDNLive! EMEA (Europe, Middle East, and Africa) May 3-5 in Munich. The technical user conference examines the technologies and methodologies for realizing EDA360. The Cadence event features best practices on critical design and verification issues, and new techniques for realizing advanced silicon, SoCs, and systems. CDNLive! EMEA also offers product demonstrations, in depth user-presented technical papers, comprehensive road map presentations, dynamic panel discussions and social networking opportunities with peers.

CDNLive! EMEA Topics

  • Comparison of Different Modeling Approaches to Assist the Mixed-Signal RF Top-Level Simulation and Functional Verification
  • How to boost Mixed-Signal Design Implementation Productivity
  • Universal Verification Methodology (UVM) 1.0
  • Take on Giga-Gate/GHz, Low-Power, and Mixed-Signal Design Challenges Using the Cadence 28nm-Ready Unified Digital Flow
  • Introduction of the new DDR3 Design-In Kit
  • PDN (Power Delivery Network Analysis) with 16.5 Allegro PCB SI
  • Choosing and Designing Low-power Memory Interfaces
  • In-Design Signoff Verification
  • Top level simulation and functional verification of the RFDAC based multi-standard transmitter
  • Hierarchical low power flow for the ARM Mali-400 MP GPU
  • OrCAD Marketplace overview
  • Breaking Down the Memory Wall Through Innovation
  • Mixed-Signal Simulation experience with Multi-Chip Module Design
  • How database access commands can make your life easier
  • What’s new in OrCAD 16.5
  • LPDDR2-NVM Phase Change Memory in Highly Integrated Cellphone Chipsets
  • VCOs Simulation using Spectre RF
  • ETS AOCV handling statistical variabilities
  • What’s new in Allegro 16.5
  • A New Breed of NAND Flash Simplifies System Designs
  • Using ESL models in functional verification
  • FlexRay Conformance Testing using OVM
  • Implementation strategies for a high performance Cortex-A15
  • Behavioral Modeling facilitates Chip-Package Codesign
  • Implementation of a Post-Layout Optimization method with Automatic Device Type Selection within practical analog circuit design processes
  • Advanced e Language Debugging – An IDE Perspective
  • Migrating a front end flow to RTL Compiler, and application to a 28nm wireless IP
  • Advances in Creepage and Air Gap Analysis in Electromechanical Products with NEXTRA
  • Memory Subsystem Integration Signal Integrity Considerations
  • Design of a Continuous-Time Sigma-Delta Modulator for Bluetooth
  • DMS as quality improvement for complex mixed signal power management designs
  • Logic Equivalence Checking is not always logical and may not be equivalent
  • Physical Implementation of Analog Circuits Assisted by Conventional Digital Place and Route Methods
  • Mastering mixed signal IC with Cadence Encounter Digital Implementation
  • Speeding up the development of register assertions by re-using functionality from an interface
  • Low-Power Design Challenges: An Implementation Perspective
  • Development of Mixed Signal Design Kits and Workflows to improve design productivity of ASICs for applications on large scale Particle Physics
  • Overlapping timing verification at the interface of Custom and Digital Design
  • Successfully Migrating SoC Verification Environments into the UVM Library
  • Important ECOs implementation using gate-array-like mask configurable cells
  • DEF File Export Considering Overlapping Structures
  • Keeping Bugs From Being Checked-in With Automated Change Management Technology
  • Design Flow for High Level Synthesis of Digital Signal Processing Algorithms from Simulink Models
  • Implementation of an RF-DAC based multistandard transmitter system
  • Advancements in Reliability Simulation
  • Experiences in Developing and Using OVM and UVM VIP
  • SoC Architecture Analysis with ARM Fast Models
  • Enabling advanced IC6.1 features and flows using X-FAB design kits
  • Using ISX GDB Server for Software Debugging on a Simulated STMicroelectronics Processor
  • Developing a generic and configurable testbench to verify different CPU architectures
  • Implementation Aspects of a 3D DfT Architecture
  • ISX HW-SW co-verification challenges on a 16-bit microcontroller system
  • The Application of Layout Module Generators upon Circuit Structure Recognition
  • Industry Needs a New Mixed Signal Design and Sign-Off Simulation Flow
  • Verification Efficiency, Quality, and Productivity Through Consistency
  • Overview: A Standard Cell Development flow for new Technology/PDK Turn On

Register: CDNLive! EMEA