Tanner EDA to Host Three Webinars

Tanner EDA announced three webcasts for April. The HiPer Verify webinar will take place April 5th and will explain how to the HiPer Verify DRC/ LVS tool to run verification throughout the design cycle to ensure error-free and timely tapeouts. The L-Edit webinar will take place on April 14th and show how to use L-Edit to reduce the unpredictable costs and workload related to a tapeout deadline. The HiPer DevGen webinar will take place April 21st and will demonstrate how to reduce weeks of design time into minutes for current mirrors, differential pairs, and/or resistor arrays in analog designs.

High Performance Physical Verification Tools for a Best Practices Workflow Webinar
April 5, 2011: 9:00-10:00 am PDT
It is no secret that a best practice workflow is to have iterative verification throughout the design cycle. The high price of “gold standard” physical verification tools often forces designers to work with short-term licenses and postpone their verification phase to the very end of design and layout. This creates risk and uncertainty that can lead to errors in tape out and respins that ultimately delay time to market. Learn how Tanner EDA’s HiPer Verify works to promote — rather than distort — a designer’s natural physical layout workflow and mitigate risk and uncertainty while reinforcing an iterative verification methodology.

Analog Layout Productivity Webinar
April 14, 2011: 2:00-3:00pm PDT
With pressure to reduce time to market and with resources increasingly constrained, tools that can enable maximum productivity are mission-critical. Tanner EDA’s L-Edit for physical layout is a powerful, robust layout editor that is so easy to use it requires virtually no learning curve to get started.

Analog Layout Acceleration Live Tool Demonstration Webinar
April 21, 2011: 2:00-3:00pm PDT
Tanner EDA will present a game-changing approach to accelerating analog IC layout. The online seminar will introduce their newly released industry-leading tool for device generation, HiPer DevGen (High Performance Device Generator). The tool integrates seamlessly with their L-Edit layout editor and improves productivity. A Tanner EDA product manager will be driving the tool for a live demonstration. Attendees will see first-hand how to reduce weeks of design time into minutes using HiPer DevGen for current mirrors, differential pairs, and/or resistor arrays in an analog designs.