Synopsys DC Explorer for Early RTL Exploration

DC Explorer, from Synopsys, is a tool for early RTL exploration. DC Explorer accelerates the development of high-quality design data. The Synopsys tool tolerates incomplete design data and can be used very early in the design flow. It features 5X faster runtime and 10% timing and area correlation to DC Ultra RTL Synthesis. DC Explorer enables designers to perform what-if analyses of different design configurations early in the design cycle. DC Explorer is currently limited to select customers.

Synopsys DC Explorer for Early RTL Exploration

Synopsys DC Explorer Features

  • Enables RTL exploration for a better starting point for RTL synthesis
  • Tolerance of incomplete design data
  • 5-10X faster runtime than RTL synthesis for efficient what-if analyses
  • 10% timing and area correlation with DC Ultra (Topographical) for early visibility into implementation results
  • Generates a netlist for early design exploration and block feasibility in IC Compiler before RTL is complete
  • Script-compatible with DC Ultra for easy deployment into existing flows
  • Multicore compute platform support delivers additional 2X runtime speedup on 4 cores
  • Provides early visibility into design implementation results
  • Enables designers to conduct what-if analyses of various design configurations early in the design cycle
  • Speeds the development of high quality RTL and constraints
  • Drives a faster, more convergent design flow

More info: Synopsys