Cadence Wide I/O Memory Controller IP Core

Cadence Design Systems introduced a licensable, wide I/O memory controller core for mobile applications like smartphones and tablets. The new Cadence IP core delivers up to four times the performance of conventional memory interfaces. The wide I/O memory controller and supporting VIP are available now. According to Cadence, the IP is already in use by a high-profile customer on two separate projects.

Cadence Wide I/O Memory Controller IP Highlights

  • Offerss PC-like performance for mobile applications like smartphones and tablets
  • Up to four times the performance of conventional memory interfaces
  • Meets the performance metrics of the proposed wide I/O specification
  • Complemented by memory models, verification IP (VIP) and a 3D IC design methodology
  • Lowers the risk and overall cost of SoC design
  • Interface operates at a peak data transfer rate of 12.8 gigabytes per second (GB/s)
  • Enables an array of low-cost and low-power connections between an application processor and the DRAM stacked on top of it
  • Enables higher bandwidth with less power while also meeting the goals of reduced PCB area and component height
  • Designed to enable maximum system-level performance
  • Includes algorithms to ensure highly efficient data transfer and to intelligently schedule transactions
  • Can reorder traffic by monitoring system transactions and delineate between low priority and system critical tasks
  • Minimizes latency on critical transactions
  • Traffic sensing to automatically adjust the power consumption based on the type of traffic
  • Supports operation at multiple frequencies
  • Dynamic voltage and frequency scaling (DVFS) for lowering power
  • Can be custom fitted for each SoC — reduces time-to-market and risk

More info: Cadence Design Systems