Dolphin Integration is offering a VHDL-AMS modeling training workshop in April. The VHDL-AMS Modeling training event will present the language constructs of either Verilog-AMS or VHDL-AMS. It covers techniques for creating and validating behavioral models. Designers will learn how to perform bottom-up modeling through structural assembly of behavioral models for multi-level simulations. The seminar is ideal for designers involved in mixed-signal electrical designs and/or analog behavioral modeling and simulation.
VHDL-AMS Modeling Training Topics
Introduction to VHDL-AMS
Designers are presented with an overview of the language including mixed-signal modeling and simulation techniques with VHDL-AMS. The designers will also assess what is possible to do with VHDL-AMS compared to SPICE. The concept of equivalence classes will be explained so that designers get sensitized to identifying which device characteristics need to be modeled depending on the application.
VHDL-AMS statement extensions to VHDL
This topic will cover the statements added to VHDL to enrich the event driven approach to continuous time and to the statements supporting the implementation of ordinary differential equations.
Time domain modeling
Dolphin Integration will explain how to perform time domain modeling, including initial conditions, handling of discontinuities and time step control.
Frequency domain modeling
The seminar will show how to extract the magnitude and the phase of a signal depending on the frequency.
Transfer function based modeling
The workshop will explain how to replace filter circuits by a simple function representing its behavior for continuous and sampled systems.
Diverse VHDL-AMS specific modeling hints
Dolphin Integration will teach how to exchange data with I/O file, create function repositories with packages and generalize functions with operator overloading.
This topic will cover two hierarchical modeling techniques: source level hierarchy for behavioral modeling and schematic level hierarchy for structural assembly.
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