New Version of SynaptiCAD TestBencher Pro

SynaptiCAD rolled out a new verion of TestBencher Pro, which is a VHDL and Verilog system-level testbench generation software. The tool simplifies the process of creating and applying random bus transactions to RTL and gate-level models. The latest version of TestBencher Pro simplifies the creation of testbenches that reside in a different compiled library from the design being tested.

SynaptiCAD TestBencher Pro VHDL and Verilog system-level testbench generation software

New TestBencher Pro Features

  • Simplifies creation of testbenches that reside in a different compiled library from the design being tested
  • Updated version of BugHunter Pro graphical HDL debugger
  • Improved support of ModelSim and Incisive simulators on Windows and Linux platforms
  • Eliminates many of the manual coding steps that were previously required to create a testbench that applies a set of weighted-random transactions with contrained-random input data to a model under test
  • A fully randomized testbench with uniform transactor weightings can now be created without manually writing a single line of HDL code

More info: SynaptiCAD