Arteris and EVE Design Flow for System-on-Chip Development

Arteris and EVE teamed together on an integrated solution for system-on-chip (SoC) developers. The design flow enables engineers to generate and use actual SoC register transfer level (RTL) implementations on EVE’s ZeBu-Server emulation platform. The integration flow helps SoC developers create and ship products sooner.

Arteris and EVE Design Flow for SoC

  • Integrates NoC interconnect creation and deployment with hardware emulation
  • Interconnect IP for the complete SoC can be assembled in Arteris FlexNoC, where the RTL is generated for input into the EVE Zebu emulation platform
  • Simplifies architectural exploration and testing
  • Enables multiple test iterations in a single day using the actual applications that will be run on the final SoC
  • Easily test the impact of different cache sizes and the number of computing cores on metrics like latency and bandwidth
  • Quickly iterate tests on EVE Zebu while using the exact same NoC interconnect we will use on the finished silicon SoC
  • Enables SoC designers to make the most efficient use of silicon area and power, and optimize software performance based on actual data traffic information
  • Ideal for for mobile and wireless SoC devices

More info: Arteris | EVE