This year’s DATE 2011 conference will feature two educational technical workshops hosted by Apache Design Solutions. The Chip-Package-System Methodology from Early Stage to Sign-off workshop will take place on March 15th. The Power Methodology for Energy Efficient Designs workshop will take place March 16th. Apache Design Solutions will also present two technical papers at DATE: Ball Grid Array Packages Electrical Optimization Using Apache Package Modeling Tools and System Level Power Integrity Analysis and Supply Network Optimization of a Dual Core CPU.
Apache Technical Workshops and White Papers
Chip-Package-System (CPS) Methodology from Early Stage to Sign-off
Tuesday, March 15, 14:00 – 15:00
This workshop will discuss the impact of power and noise on overall system cost and performance and how a proven Chip-Package-System (CPS) methodology, deployed from early in the designs stage and throughout the flow to sign-off, will address the power integrity and power induced noise challenges faced by engineers. It will detail the modeling, extraction and analysis technologies, and efficient model exchange capabilities required for bringing together the SoC, IC package, and system designers in meeting their system cost and performance targets.
Power Methodology for Energy Efficient Designs
Wednesday, March 16, 12:30 – 13:30
This technology workshop will demonstrate a power methodology highlighting Apache’s portfolio of power and noise analysis platforms to address the needs of low power, energy efficient designs. It will include details of RTL power analysis, reduction and debug, custom IP validation and model creation, and SoC integration, optimization and sign-off, to ensure that the required power budget is met while maintaining its design integrity. The presentation will also touch on advanced reliability challenges such as ESD and 3D IC, with respect to power, signal and thermal integrity.
Ball Grid Array Packages electrical optimization using Apache package modeling tools
Wednesday, March 16, 10:30 – 10:50
This paper will discuss the effects of constraints on real package designs, in term of application speed, bandwidth of signals, and impact on the margins. It will also explain why the package designer counterparts are requesting new tools that can bridge several parts of the system to ensure a full system optimization.
System level power integrity analysis and supply network optimization of a dual core CPU
Thursday, March 17, 10:10 – 10:30
This paper will discuss the methodology and flow used to perform a CPU core power integrity check at the core block level within the system level context. It will also explain how to extend the flow to package analysis still within a system level context. The paper will demonstrate the use of Apache Design Solutions tools for model extraction and power supply analysis at the system level.