Synopsys DesignWare IP for PCI Express 3.0

According to Synopsys, it is the first IP provider to support the final version of the PCI Express (PCIe) 3.0 base specification (version 1.0). DesignWare digital controllers for PCI Express now also support the latest PIPE 3.0 specification (v0.9), PCI-SIG Engineering Change Notifications (ECNs), 256-bit datapath and embedded DMA engine. Synopsys’ DesignWare IP for PCI Express 3.0 is available now.

Synopsys DesignWare IP for PCI Express 3.0 Highlights

  • Supports the final release of the PCIe 3.0 base specification (version 1.0) released by the PCI Special Interest Group (PCI-SIG)
  • Optional ECN support enables power reduction and increases performance for specific applications
  • Supported ECNs include TLP Processing Hints, ID Based Ordering, Atomic Operations, BAR Resizing, Extended TAGs, Latency Tolerance Reporting (LTR) and Optimized Buffer Flush/Fill (OBFF)
  • New 256-bit datapath targets SoCs for the enterprise computing market that require a 16 lane (x16) PCIe 3.0 interface
  • 56-bit datapath can handle multiple packets arriving in a single clock cycle
  • Offers performance advantage over other solutions that simply scale the data bus of a 64-or 128-bit controller
  • Embedded DMA engine offloads the main SoC processor when moving large amounts of data between the PCIe interface and the rest of the system
  • Improves system performance and latency
  • Embedded DMA engine supports the native application interface or ARM AMBA AHB and AXI3 bridges
  • Supports multiple channels, interleaving, linked list and full duplex operation

More info: Synopsys DesignWare IP