Design and Verification Conference 2011

The Design and Verification Conference (DVCon) will take place Monday, February 28 through Thursday, March 3 at the DoubleTree Hotel in San Jose, California. Keynote and featured panels include: From Volume to Velocity, Making Great Products Great, and VM — Final Answer or Phone a Friend? The event is sponsored by Accellera, which is an industry consortium dedicated to the development and standardization of design and verification languages.

DVCon Keynote, Presentations, Tutorials, Panels and Sessions

  • From Volume to Velocity Keynote
  • UVM – Final Answer or Phone a Friend?
  • Making Great Products Great
  • A Functional Verification Journey: Stop Spinning in Circles
  • Industry Leaders Verify with Synopsys
  • UVM Workshop
  • Software-driven Verification Using SystemC TLM-2.0 Virtual Platforms
  • Good Fences Don’t Make Good Neighbors
  • Advanced SoC Verification with SystemVerilog and TLM-2
  • Advanced Verification Technologies in the Real World
  • Stress Free Assertion Based Verification
  • UVM in Real Life
  • New Frontiers in Verification
  • Mixed Signal Verification
  • UVM Enhancements
  • Acceleration Techniques
  • Pragmatic Approaches to Verification
  • Low Power Verification
  • Vertical Reuse
  • UVM Applications
  • Coverage Driven Verification
  • Automated Techniques
  • Case Studies

More info: DVCon Conference Registration | Accellera