Synopsys Enhanced DesignWare Universal DDR Memory Controller

Synopsys enhanced their DesignWare Universal DDR Memory Controller (uMCTL2). The enhanced version offers up to 30% lower latency and up to 15% higher throughput than the previous generation controller. The enhanced uMCTL combines the previous-generation DesignWare Universal DDR memory controller with the the Intelli architecture acquired from Virage Logic. The enhanced version of the DesignWare Universal DDR Memory Controller single-port configuration will be available next month.

Synopsys Enhanced DesignWare Universal DDR Memory Controller (uMCTL2)

Synopsys Enhanced uMCTL Features

  • Up to 30 percent lower latency
  • Up to 15 percent higher throughput
  • High-priority bypass and configurable look-ahead features
  • Improves latency by bypassing the scheduling algorithm
  • Enables immediate access to the DRAM
  • Intelligent scheduling to maximize throughput by prioritizing out-of-order transactions to the DRAM
  • DFI 2.1-compliant interface to the DDR PHY
  • Memory system performance of up to 2133 Mbps
  • Supports the DDR3, DDR2, LPDDR and LPDDR2 SDRAM standards
  • Integrated, single-vendor DDR solution when combined with Synopsys’ DesignWare DDR PHY
  • Supports soldered on DRAM or DIMM DDR subsystems
  • Supports up to 4 ranks of DRAM
  • Host interface slave for easy integration with an external arbiter or standard on-chip buses
  • Efficient DDR protocol implementation leveraging out-of-order transactions to maximize data throughput, while instilling starvation avoidance and guaranteeing data coherency
  • Programmable memory initialization
  • Optional ECC module supporting Single Error Correct (SEC)/and Double Error Detect (DED)
  • Read Modify Write Support
  • APB interface for software accessible registers
  • Provides a method for testing large sections of memory

More info: Synopsys