Cadence Digital End-to-end Flow for 28nm Giga-gate/Gigahertz Designs

Cadence Design Systems announced a 28nm digital end-to-end design flow based on Encounter. The digital 28-nanometer flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. The new Encounter-based flow enables designers to consider the entire chip flow holistically. It supports Cadence’s approach to Silicon Realization, which is a key element of the EDA360 vision. The new flow is available now.

Cadence 28nm Digital End-to-end Flow Features

  • Complete, silicon-proven 28nm design rule intent (electrical, physical, DFM) with early, upfront tradeoff analysis
  • 2x improvement in routing runtime through intelligent via and pin-density optimizations
  • Eliminates the need for tradeoffs between complexity and advanced process nodes
  • Works seamlessly with Cadence’s analog/mixed-signal and silicon/package co-design domains
  • Early clock topology intent capture and planning that uses physical information to intelligently optimize clock gating and balance clock trees throughout the design during synthesis
  • Data abstraction technologies enable entire blocks of logic to be modeled simply and accurately, and optimized across logical and physical domains, for giga-gate scalability and design productivity
  • Support for hierarchical low-power and OpenAccess-based mixed-signal quick/detailed abstractions to enable rapid integration of IP and advanced SoCs
  • A physically aware pre-mask functional ECO capability that automates difficult to implement functional ECOs, providing faster convergence and dramatically shortening the design cycle
  • Architecture for in-design advanced analysis that provides ultra fast one-step signal integrity and timing analysis closure during the design flow for efficient design convergence
  • Accurate full mixed-signal static timing analysis and timing-driven optimization to reduce iterations between analog and digital design teams
  • New fully-integrated 3D-IC capabilities with unified intent, abstraction, and convergence spanning digital, full-custom, and package design
  • Includes Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Conformal technologies, Encounter Test, Encounter Timing System, Cadence QRC Extraction, Encounter Power System and Encounter DFM technologies

More info: Cadence Design Systems