Jasper ActiveProp Property Synthesis

ActiveProp, from Jasper Design Automation, is an innovative new property synthesis tool. ActiveProp helps accelerate the adoption of assertion-based verification, including formal verification and simulation. ActiveProp automates the creation of properties and produces high-quality results faster. ActiveProp improves verification efficiency for any assertion-based verification flow. ActiveProp is available now.

ActiveProp Property Synthesis Features

  • Automatically generates high-level properties in SystemVerilog Assertion (SVA) language
  • Human-readable reports from RTL and simulation information
  • Helps expand the verification property set
  • Increases functional coverage
  • Identifies coverage holes
  • Higher-quality chip designs
  • Generates intelligent, high-quality properties (assertions, constraints and covers) automatically
  • Multiple simulation runs can further refine the intelligence of generated properties
  • Unique multi-cycle analysis contributes to property quality, and generates properties where the causal effects are far removed from the resulting effects
  • Handles hierarchy, extracting properties across different modules and levels of hierarchy
  • Inputs are RTL, simulation information and scoped signals of interest which the user can control
  • Any simulation or testbench, block, system-level, or full SoC, can be used as input
  • Simulator input can be provided in two ways, either running ActiveProp on previously created simulation files, or linked during run time with the simulator
  • Outputs industry-standard SVA properties, which are used in any assertion-based design and verification flow
  • Pre-defined checks including static checks
  • Checks for common design errors such as arithmetic overflow, bus conflicts and illegal clock-domain crossings
  • Coverage checks for errors such as dead-end and unreachable states

More info: Jasper Design Automation