RTL-to-GDSII Silicon Realization Reference Flow for Common Platform

Cadence Design Systems announced a qualified 32/28-nanometer reference flow for the Common Platform technology. The new Silicon Realization reference flow for the Common Platform alliance is built around the Cadence end-to-end Encounter flow, including Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and Encounter Power System.

Cadence Silicon Realization Reference Common Platform Flow Highlights

  • Comprehensive flow from RTL synthesis to GDSII signoff for the advanced node, low-power high-k metal gate (HKMG) process technology
  • Built around the Cadence end-to-end Encounter flow
  • Includes Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and Encounter Power System
  • Validated using the 32/28-nanometer ARM low-power physical libraries
  • Employs the Common Power Format (CPF)-enabled Cadence Low-Power Solution to maintain power intent throughout the design process
  • Includes physically aware synthesis, large-scale rapid design exploration and physical prototyping, advanced timing and signal integrity concurrent optimization with multi-mode and multi-corner analysis and optimization, context-aware placement, advanced OCV-aware clock tree synthesis, litho-aware routing, and in-design signoff analysis for timing and power
  • Concurrent design for manufacturing (in-design DFM) technology is enabled on demand to ensure manufacturability at 32 and 28 nanometers
  • Optimized for power savings

More information: Cadence Design Systems