New Cadence Capabilities for FPGA and ASIC Designs

Cadence Design Systems introduced over 600 new capabilities to improve verification productivity for ASIC and FPGA designers. The capabilities, along with support for the Accellera Universal Verification Methodology (UVM), will expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.

New Capabilities Highlights

  • Boost verification productivity for ASIC and FPGA designers
  • Expand the scope of metric-driven verification (MDV)
  • Help engineers achieve faster, more comprehensive verification closure and Silicon Realization
  • Target inefficiencies that exist in verification flows for many advanced node designs
  • Bind fractured verification flows through MDV
  • Verification engineers can merge coverage data from formal analysis and simulation engines within a unified verification plan
  • Support for enhanced low-power corruption and isolation simulation
  • Automation for combining and mixing simulation and formal technologies
  • Earlier bug detection is enabled through additional abstraction capability
  • Support of the UVM 1.0 standard for testbench verification
  • Improving engine performance enables faster convergence of the verification process to the verification plan
  • Incisive Specman Advanced Option provides reseeding and dynamic loading of e-based tests, multi-core e code compilation
  • Shorten debug mixing interpreted and compiled code improving overall productivity by greater than 1.4 times
  • Support for multi-core formal analysis
  • 1.3-times faster SystemVerilog testbench simulations

More info: Cadence Design Systems