GiDEL TotalHistory for ASIC Prototyping and FPGA Debug

TotalHistory, from GiDEL, is a software only solution that enables engineers to have visibility of any signal in their designs, for virtually unlimited trace depth, with no or minimal degradation in performance. TotalHistory is available with GiDEL’s PROC_SoC ASIC Prototyping Systems and PROC Boards FPGA-based High Performance Computing (HPC) accelerators.

With TotalHistory, designers can define a list of signals in the design which they want to trace at full system speed. There is practically no limit on the number of signals traced. The developer can view the trace using a waveform viewer to debug and validate the design. Optionally, an API is available for queries by advanced users.

More info: GiDEL | Kane Computing