Imec recently revealed their CMOS research in scaling logic, DRAM and non-volatile memory. A new device based on non-silicon channels was realized to scale high-performance logic towards the sub-20nm node. In addition, imec developed low-leakage capacitors enabling DRAM to be pushed to the 2x nm node. Imec also shared their research on the switching mechanism of resistive RAM for next-generation flash memories (RRAM). The results were obtained in cooperation with imec’s key partners in its core CMOS programs: Intel, Micron, Panasonic, Samsung, TSMC, Sony, Fujitsu, Infineon, Qualcomm, ST Microelectronic and Amkor.
Implant-free SiGe channels to scale logic ICs towards the sub-20nm node
Imec developed a new implant-free SiGe (silicon germanium) quantum well pFET device featuring a high-mobility SiGe channel with raised SiGe source/drains using bulk-Si substrates. The high-electron mobility transistor with an EOT (effective oxide thickness) of 0.85 achieves a 50% higher saturation drive current compared to Si-controlled pFETs. The device concept is compatible with additional strain boosters paving the way to deep-submicron scaling achieving high performance.
Low-leakage MIM (metal insulator metal) capacitors enabling 2x nm node DRAM
Imec scaled DRAM to the 2x node by using novel stack engineering. To scale DRAM to the 2x nm node, low leakage at an EOT of 0.4nm and less is required, deposited with highly conformal atomic layer deposition (ALD) processes for compatibility with large aspect ratio structures. Imec announced record low-leakage MIM capacitors, JG of 10-6 A/cm2 at 0.4nm EOT, that can scale DRAM to the 2x nm node. The capacitors were realized using a novel TiN/RuOx/TiOx/STO/TiN stack fabricated in a 300mm line with DRAM compatible processes.
Fundamental understanding of switching mechanism of RRAM
Imec applied its reliability knowledge of logic to RRAM, resulting in fundamental understanding of the switching mechanism of RRAM. By finding synergies between conventional logic ICs and RRAM, imec succeeded in setting out the theory for predicting the maximum applicable Vset and revealed that the reset operation corresponds to a pinch off of the filament at its narrowest point. RRAM is a promising alternative concept for future flash memory.
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