White Paper: Memory Subsystem Model for Evaluating Network-on-Chip Performance

Open Core Protocol International Partnership (OCP-IP) published a white paper titled “A Memory Subsystem Model for Evaluating Network-on-Chip Performance.” The technical paper discusses performance characteristics of DRAM memories that affect NoC evaluation. Work on the white paper was completed by the OCP-IP Network on Chip Benchmarking Working Group led by Tampere University of Technology and Sonics Inc.

The white paper includes a set of parameters that can be used to generate a highly abstracted DRAM controller and memory at an abstraction level high enough to make development easy, while still capturing those critical parameters that significantly influence system performance. The values of the parameters can be obtained from the JEDEC standards for the desired DRAM memory. Based on these values, the memory model can inject transaction-specific latencies. The model described enables system architects to get a more realistic picture of their system and thus helps design the NoC as part of the system as opposed to treating the NoC in isolation.

The OCP-IP memory modeling technical paper concludes by stating System-on-Chip designs incorporating a NoC are constrained by limited memory efficiency. As a result, performance analysis of the NoC that is agnostic to the memory requirements may result in overly optimistic results, which may not be reproducible in the real system once the DDR memories are incorporated. Performance analysis in memory agnostic environment can therefore result in surprises late in the design cycle, and possibly a requirement to re-architect the NoC due to the performance implications of the memory subsystem. This will significantly delay the time to market of the SoC.

More information: OCP-IP Memory Modeling White Paper (pdf)