Synopsys DesignWare ARC AS 221 Processor Core for Bluray Disc Players

A couple of announcements by Synopsys yesterday: (1) DesignWare ARC AS 221 BD dual-core processor has been optimized for high-definition (HD) audio applications and (2) three new enhancements to their DesignWare ARC 600 32-bit configurable processor family. The DesignWare AS 221 BD and the new enhancement options to the DesignWare ARC 600 family cores are available now. Synopsys’ DesignWare ARC cores enable engineers to lower integration risk and speed time-to-market for their embedded system-on-chip (SoC) designs.

DesignWare ARC AS 221 BD Dual-core Processor

  • Optimized for high-definition (HD) audio applications
  • Ideal for SoCs targeting Blu-ray Disc and Pulse Code Modulation (PCM) 192 kHz/24-bit digital audio streaming applications
  • Extends Synopsys’ DesignWare Sound-to-Silicon AS 200 processor family
  • High-performance dual-core processor
  • Includes complete software stack
  • Features all the required codecs, media streaming framework, and Blu-ray Disc use cases
  • Includes all the memories required to run the full Blu-ray software stack
  • Processor occupies 0.81 mm2 in a 65-nm LP process, up to half the size of alternative solutions
  • Processor’s power consumption (0.26 mW/MHz) is up to one-and-a-half to three times more power efficient than existing solutions

DesignWare ARC 600 32-bit Configurable Processor Family Enhancements

  • Full range of configurable and extensible 32-bit cores ranging from full-featured to ultra-compact configurations
  • Utilize a 16-/32-bit instruction set architecture (ISA)
  • Provides both reduced instruction set computing (RISC) and full digital signal processing (DSP)
  • Easy to use, unified architecture
  • The Memory Protection Unit (MPU) for the DesignWare ARC 610D and 625D cores gives software running on the core the ability to control access rights to the memory
  • The optional Power Management Unit (PMU) for the DesignWare ARC 605, 610D and 625D cores enables application software control over clocking and voltage for the core, allowing dynamic power consumption management
  • The optional single-cycle 16×16 multiplier is available for the DesignWare ARC 601, 605, 610D and 625D cores reduces power consumption and silicon area for applications that do not require the processing speed of a 32×32 multiplier

More information: Synopsys