Cadence to Present at ARM Technical Conference 2010

Cadence Design Systems will presenting at the ARM Technical Conference (TechCon) 2010. John Bruggeman (Cadence Chief Marketing Officer and Senior Vice President) will participate in a chat with Simon Segars (ARM executive vice president and general manager of the Physical IP Division). The chat, The Electronics Industry is Evolving, will discuss how ARM and Cadence are playing key roles in leading the revolution in innovative products and approaches to design. The chat session will take place from 5:00 p.m. to 5:45 p.m. on Tuesday, Nov. 9, 2010. Cadence will also present several technical sessions and papers at the ARM conference. The ARM Technology Conference will take place at the Santa Clara Convention Center November 9-11, 2010.

Cadence Sessions at TechCon

  • Keys to Silicon Realization of Gigahertz Performance and Lower Power ARM Cortex-A15
    This session features Rob Lipsey, distinguished engineer at Cadence; Gopi Kudva, senior product engineering manager at Cadence; and Andrew Lambert, principal implementation engineer at ARM. This session will highlight key considerations in the implementation of ARM’s new Cortex-A15 MPcore processor and will describe advanced design techniques used in an RTL-to-GDSII digital implementation reference methodology.

  • Are System Developers Ready for Applications to Drive and Define a New World Order?
    This panel, hosted by Ron Wilson, director, content and media for events, EE Times Group, will feature panelists from Broadcom, Linaro, TSMC, Xilinx and Cadence, who will debate several aspects of system realization and evaluate key issues that will directly impact system-level design and hardware/software integration.

Cadence Technical Papers at TechCon

  • Reliability Analysis for the Nanometer Era
  • Performance/Accuracy Tradeoffs Using TLM2 Standard Virtual Prototypes
  • Best Practices in ARM-Based SoC Power Management Verification
  • Design for Reliability with Circuit-Level Simulation
  • AMBA-Based Design, Synthesis, and Functional Verification from TLM through RTL
  • Building Integration-Optimized IP for SoC Designs
  • DFM: Starting with the End in Mind and In-Design
  • Mixed-Signal Assertion-Based Verification
  • Prevent Problems with Timing Constraints when IPs Combine
  • Layout-Dependent-Effect (LDE) Variability Design
  • Verification Solutions for Digitally Calibrated Analog Design

More information: Cadence Design Systems