Synopsys DesignWare STAR ECC IP

Synopsys’ DesignWare STAR Memory System product family now features Self-Test and Repair Error Correcting Codes. The DesignWare STAR ECC IP is a configurable IP solution that enables designers to achieve a higher level of protection against transient errors compared to the classic ECC approach and deliver a more reliable product to the market. The DesignWare STAR ECC IP is designed to provide optimal performance of partial word writes and improved error detection/correction capability in multi-bit upsets and random bit errors.

Self-Test and Repair Error Correcting Codes IP Overview

  • Enables designers to select the desired level of fault tolerance
  • Generates the corresponding IP through the STAR ECC Compiler
  • Helps system-on-chip (SoC) designers quickly reduce the number of embedded memory transient errors (such as soft errors)
  • Provides optimal performance of partial word writes and improved error detection/correction capability in multi-bit upsets and random bit errors
  • Offers five types of error code correction including:
    • Single Error Detection (SED)
    • Single Error Correction (SEC)
    • Single Error Correction with Double Error Detection (SEC_DED)
    • Single Error Correction with Force Error Detection (SEC_FED)
    • Single Error Correction with Double Error Detection and Force Error Detection (SEC_DED_FED)
  • Enables designers to achieve high performance and high field reliability while improving time-to-market
  • Offers a highly automated design implementation and test diagnostic flow
  • Ideal for automotive, aerospace and high-end computing applications
  • Enables designers to achieve a higher level of protection against transient errors compared to the classic ECC approach

More information: Synopsys