Cadence Silicon Realization Webinars

Cadence Design Systems is offering a series of silicon realization webinars. The webcasts will present new approaches to improving productivity, predictability, and profitability. Attendess will learn how to maximize investment in the UVM, find out how to achieve a predictable and convergent path to closure, learn how to eliminate bugs with formal verification, and enhance design team collaboration. All the online seminars will take place from 10am-11am PST.

Cadence Silicon Realization Webinars Schedule

  • October 20
    DRC+ Now: Early DFM Signoff in the Custom Implementation Process
  • October 21
    DRC+ Now: Early DFM Signoff in the Digital Implementation Process
  • November 2
    Why Cadence Has the Best UVM Solution
  • November 9
    Metric-Driven Verification: The Galaxy Beyond Just Simulation
  • November 10
    Parasitic-Aware Design: A Complete Flow
  • November 11
    Maximizing Your Investment in the UVM
  • November 11
    Remote Enablement for a Globalized Workforce – Cadence and Open Text Enable Optimized Performance
  • November 15
    New Techniques for Debugging NonEQs and Aborts in Equivalence Checking
  • November 16
    Are You Losing Sleep Over How to Perform Top-Level Mixed-Signal SoC Verification?
  • November 17
    Analog Verification – How Do You Know Your Circuit is Right? Smart Verification!
  • November 18
    Design Techniques That Make ECOs Predictable
  • November 19
    Managing Parasitics in the Front End
  • November 30
    A Practical Guide to Exploiting Optimization in Custom Design Flows
  • November 30
    How to Eliminate Connectivity Bugs with Formal Verification
  • December 1
    Managing Parasitics in the Back End
  • December 1
    Achieve the Next Level of Verification Productivity with the Specman Advanced Option
  • December 2
    IC 6.1: A Leap Forward in Productivity
  • December 2
    Silicon Diagnostics – Enabling Greater Accuracy for Fast Silicon Evaluation
  • December 3
    When IP Collides, Brace for Impact on Timing Constraints and CDC! Verify and Manage Your Timing Constraints and CDCs!
  • December 6
    Where Does Power Intent Come From? Create and Debug Power Intent for Low-Power Designs
  • December 7
    OpenPDK: What is the Goal of this Effort, and What is the Status?
  • December 8
    Migrating from VMM to the UVM
  • December 9
    Are You Ready for Your Next-Generation Analog/Mixed-Signal Product?
  • December 10
    Metric-Driven Synthesis: Collecting and Leveraging Inter and Intra Synthesis-Run Statistics to Improve Quality of Results

More information: Cadence Silicon Realization Webinar Series