Cadence Design Systems has been running their System Realization Webinar Series since last month. There are still three webcasts left in the series: Developing Software for ARM-Based Devices (October 13th), System Realization Services from Cadence (October 20th), and TSMC Reference Flow 11: ESL Focus on High-Level Synthesis (November 3rd). The online seminars address the challenges related to system level methodologies including design, verification, TLM, IP, and software integration.
Developing Software for ARM-Based Devices
October 13, 2010 (10 am – 11 am PDT)
Software content in embedded designs is growing fast to meet consumer demand for capability, integration, and mobility. Embedded devices are being released to consumers at a faster rate and semiconductor design times are shrinking, so software is becoming a significant challenge in system design and verification. Creating application software rapidly, debugging efficiently, optimizing performance and power, and completing hardware/software co-verification is more complex than ever. This webinar will present the latest solutions from ARM and Cadence for ARM-based embedded and application software creation, debug, and functional co-verification. ARM Fast Models are used to enable early software development and co-verification with Cadence Incisive SystemC simulation; the ARM VSTREAM running with the Palladium XP Verification Computing Platform enables accurate co-verification when the task requires 100% accurate co-verification with ARM cores and RTL SoCs. Both solutions share the widely used RealView Development Suite (RVDS) for software development.
System Realization Services from Cadence
October 20, 2010 (10 am – 11 am PDT)
The need for shorter time to market and optimized system design is driving the adoption of new system design methodologies using higher abstraction and accelerated system-level testing. SystemC modeling for system analysis, high-level synthesis, and virtual platforms for early software development are the most common areas in which customers are requesting help. Using real project examples, this webcast will highlight how engineers are employing new methodology and technology for system design and verification, and the benefits of using Cadence products. It will also describe various ways that Cadence Services uniquely enable customer success and adoption of these new solutions.
TSMC Reference Flow 11: ESL Focus on High-Level Synthesis
November 3, 2010 (10 am – 11 am PDT)
High-level synthesis is one of the key enables of higher productivity IP design and verification. TSMC has established a new ESL scope for their reference flow to help customers more easily adopt a methodology that increases productivity. Cadence contributed to the ESL reference flow, a part of which is enabling the adoption of high-level synthesis. The methodology focuses on creating high-level models in C, C++, or SystemC and using an interactive approach to understanding the resources and timing of the design. The online seminar will introduce the concepts of modeling for high-level synthesis and a repeatable approach to creating high-quality RTL designs that meet area, timing, and power constraints.