Corelis Runner-Lite JTAG Test Executive

Corelis introduced Runner-Lite, which is a free software test executive for performing boundary-scan testing, JTAG Embedded Testing (JET), and in-system device programming using pre-generated test plan files built for specific reference boards. Runner-Lite features unrestricted access to complete off-the-shelf JTAG structural and functional test solutions for many silicon vendor reference designs. The tool enables engineers to familiarize themselves with Corelis test capabilities and can be use as a test bench for reference board based designs.

Corelis Runner-Lite for boundary-scan testing, JTAG Embedded Testing (JET), and in-system device programming

Corelis Runner-Lite Features

  • Built-in test sequencer that automatically executes independent test steps
  • Executes structural and functional board tests via a simple JTAG connection
  • Complete ready-to-run reference design test procedures
  • Detects and isolates faults down to the net and pin level
  • Easy-to-use graphical user interface
  • Programs Flash and other programmable devices
  • Detailed fault reports and proximity diagnostics
  • Fault diagnostics are linked to a virtual PCB image
  • Identifies failures by fault type including stuck-at, open, and short
  • Double-sided PCB support
  • Powerful zoom, pan, auto-center, and filter functions
  • Netlist and parts browser highlights component, pin, and via locations

More information: Corelis Runner-Lite (pdf)