Cadence Digital Implementation and Signoff Seminar Series

The events will present the latest approaches to realizing silicon — productively and profitably. Engineers will learn about in-design signoff analysis with emphasis on timing, power, extraction, and in-design and DFM signoff at advanced nodes. Designers will also learn about the advanced technology in the latest release of Encounter Digital Implementation (EDI) System with emphasis on maximizing power savings and accelerating design closure.

Cadence Seminar Dates and Locations

    San Jose, CA – Oct 5, 2010
    Austin, TX – Oct 7, 2010

Cadence Seminar Agenda

  • 9:00 am: Registration and Breakfast
  • 9:25 am: Welcome
  • 9:30 am: Perspective on Design Challenges and Trends: ST Microelectronics
  • 10:00 am: Maximize Power Savings
  • 11:00 am: Accelerate Design Closure
  • 12 noon: Lunch with R&D
  • 12:45 pm: Overview: Advanced Technology for Digital Design Signoff
  • 1:15 pm: Integrated Signoff – Extraction
  • 1:45 pm: Integrated Signoff – Timing and SI (with live demo)
  • 3:00 pm: Break
  • 3:15 pm: Integrated Signoff – Power (with live demo)
  • 4:30 pm: In-Design and DFM Signoff at Advanced Nodes
  • 5:15 pm: Q&A with Cadence R&D

More information: Digital Implementation and Signoff Seminar Series