Cadence Design Systems is offering a series of EDA360 webinars. The digital implementation and signoff webcasts will present the latest approaches to realizing silicon, productively and profitably. The first online event, Getting Back Timing Margins: Traditional OCV Alternatives, starts today at 10am Pacific time. EDA360 supports both design creators and integrators.
Getting Back Timing Margins: Traditional OCV Alternatives
August 24, 2010: 10:00 AM – 11:00 AM Pacific
The webinar will present alternatives to traditional OCV, what is needed to employ them, and what the tradeoffs are. The webcast will provide the information engineers need to make the most informed decision, what is needed to employ them, and what the tradeoffs are.
If you’ve already designed chips at 65nm or below, you’re probably aware that traditional bulk on-chip variation (OCV) margins, while a step in the right direction, are a very pessimistic way of dealing with increased process variability. This makes timing closure difficult and leads to suboptimal quality of results. Alternatives are available including local OCV, advanced OCV, and statistical static timing analysis (SSTA), but choosing which one to use can be challenging.
Are You Ready For Silicon on Insulator Design Process? Hear from ARM and Cadence
August 25, 2010: 10:00 AM – 11:00 AM Pacific
The webcast will provide information on SOI technology and how to maximize its benefits. Designers will learn how to implement and verify analog, digital, and mixed signal SOI IP and SoCs. Engineers will hear about how Cadence and its ecosystem partners are collaborating to offer an end-to-end SOI solution and methodology.
Silicon-on-insulator (SOI) technology offers some compelling benefits over traditional bulk CMOS technologies — better chip performance per watt, smaller die size, and better scalability at smaller geometries. These advantages are why many chip makers are giving SoI technology a deeper look.
In-design Signoff; It’s All About Getting It Right the First Time
August 31, 2010: 10:00 AM – 11:00 AM Pacific
This online seminar will explain how to make the complete design flow more efficient by enabling the same signoff functionality tightly integrated with the design environment. Benefits and drawbacks of the approach will be discussed, including how designs with multiple modes of operation can be more efficiently managed.
In the past, a common methodology was to complete the design of the chip and then use separate signoff tools to ensure that the design met the specifications for timing, signal integrity, dynamic power, leakage, and IR drop. Standard interfaces such as LEF/DEF and GDSII were used to transfer the data between the design and signoff solutions, but the flow to fix any problems was complicated and clumsy because of disparate solutions.
Should You Design Your Next System With 3D TSVs?
September 03, 2010: 10:00 AM – 11:00 AM Pacific
GLOBALFOUNDRIES and Cadence will discuss the challenges associated with the design, implementation, and verification of 3D-ICs using TSVs. Learn about optimum packaging solutions to meet desired performance and cost goals. Run through a holistic, production-proven flow that enables engineers to complete thier 3D-IC design quickly.
Demand for miniaturized, low-power, and high-performance heterogeneous device applications is driving interest in a new system-in-package (SiP) approach called 3D-IC. This technique vertically stacks multiple die with through-silicon via (TSV) interconnects to provide cost, power, and performance advantages. Years ago, the question was “Why 3D?” But today, as more and more companies adopt 3D-IC technology and reap the benefits, the questions are “When 3D?” and “How 3D?”
Improving Your Yield; What to Watch Out for at 28nm and Beyond
September 07, 2010: 10:00 AM – 11:00 AM Pacific
In this webinar, attendees will learn about the impact of litho, CMP, and stress layout-dependent effects on advanced node designs, and how Cadence technologies and methodologies integrated with Virtuoso and Encounter environments enable designers to confidently and predictably deliver the highest yielding design to their foundry.
Starting at 45/40nm design, comprehending design for manufacturing (DFM) went from a “nice to have” to a “must have” and has recently been declared a mandatory step in the IC design flow. But what, when, where, and how does the designer incorporate this new optimization objective into an existing digital, analog, or mixed-signal design flow, and is it worth the extra effort?
Maximizing the Performance-Per-Watt of Your Next Design
September 09, 2010: 10:00 AM – 11:00 AM Pacific
This webcast will explore the different options available to reduce power from both a leakage and dynamic aspect. Techniques such as multiple threshold voltage optimization and clock gating strategies will be discussed, as well as more advanced power management options such as power shutoff, multiple supply voltages, and dynamic voltage/frequency scaling. The webinar will also explore the use of cutting-edge techniques like dual/quad flops to help you streamline chip performance.
In two short years, power requirements have matured from a “nice to have” criteria to a mandatory consideration designs. Today’s low-power chips are expected to be power efficient while retaining the performance comparable to previous powerhouse designs. But how do you achieve both higher performance and lower power? Managing performance-per-watt is the key.