Aldec introduced ALINT 2010.06, which is a design rule checking software solution. ALINT 2010.06 features a phase-based linting (PBL) methodology that provides structured and prioritized phases for the analysis of HDL design issues. The design rule checking tool reduces the number of linting iterations and error messages at each phase. ALINT eliminates more design issues incrementally at each phase. Default phases may be modified or customized by engineers for adherence to corporate design policies or conducting targeted design rule checks. The latest release of ALINT is available now. The tool supports STARC, RMM, DO-254 and Aldec design rule plug-ins, which are sold separately.
Aldec ALINT 2010.06 Features
- Fast design analysis of complex ASIC/FPGA/SOC designs
- Phase-Based Linting (PBL) Methodology
- IEEE VHDL, Verilog and mixed-language designs
- STARC VHDL or Verilog rule plug-ins
- DO-254/ED-80 VHDL or Verilog rule plug-ins
- RMM rule plug-in
- Custom rule creation
- Integrated result analysis and debugging environment
ALINT 2010.06 supports STARC (Semiconductor Technology Academic Research Center), RMM (Reuse Methodology Manual) and DO-254 best practice design rules that define a methodology for efficient reuse and verification of System-On-A-Chip (SoC), ASIC and large FPGAs. ALINT checks VHDL, Verilog and mixed-language designs for structural, coding and consistency issues prior to simulation and synthesis, which can significantly reduce verification time of complex FPGA and ASIC designs.
More information: Aldec