DVCon 2011 Issues Call for Papers, Panels, and Tutorials

The 2011 Design and Verification Conference (DVCon) is seeking paper and panel abstract submissions and tutorial proposals. Paper and panel proposals are due August 31, 2010. Sponsored tutorial proposals are due September 16, 2010. DVCon 2011 will be held February 28 to March 3, 2011 at the DoubleTree Hotel in San Jose, California. DVCon is sponsored by Accellera, an industry consortium dedicated to the development and standardization of design and verification languages.

DVCon Topics of Interest

  • Experience using ESL and/or TLM for system-level design and verification
  • Experiences deploying a verification methodology library
  • Experiences with System-on-Chip design
  • Designing and/or verifying complex ASICs and FPGAs
  • Using multiple HDLs and/or HVLs in a design cycle
  • Techniques for generating constrained-random test, or other automated stimulus generation methods
  • Synthesizing transaction-level or abstract designs from high-level languages such as SystemC, System Verilog or C++, to RTL
  • Experiences with hardware/software co-design and co-verification
  • Experiences with mixed-signal simulation
  • Verification techniques that really work (and what did not work)
  • Verification process and resource management
  • Assertion-based verification
  • Coverage-driven verification
  • Design and verification IP experiences, good and bad
  • Any topic involving the use of an HDL or HVL
  • Debug techniques for HVL testbenches and complex software-style testbenches
  • Debug techniques for SoCs with black-box and grey-box IP
  • Debug techniques for ESL and abstract models
  • Software engineering techniques for advanced testbenches focusing on efficiency for scalability
  • Experience with formal and semi-formal techniques

DVCon is a conference for the discussion of the functional design and verification of electronic systems.The event focuses on the use of specialized design and verification languages. The show is ideal for designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development, and application of Electronic Design Automation tools.

More information: Design and Verification Conference