Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.
This integrated RTL-to-GDSII reference flow is based on Talus 1.1, the current release of Magma’s IC implementation system, and leverages Talus Design for synthesis, Talus Vortex for physical design and Talus Power Pro for power optimization. The reference flow supports power intent through the UPF standard, incorporating multiple voltage domains, retention cell management, insertion of automatic level shifters and isolation cells, power switches, well tap cells and on-chip variation. Talus 1.1 also supports the CPF standard for power intent.
To validate the flow, a reference design incorporating Virage Logic SiWare standard-cell and SiWare memory IP was implemented in the Talus system using a UPF-compliant low-power design intent specification. The reference design met GLOBALFOUNDRIES’ technical specifications including all low-power requirements.
SiWare Memory compilers and SiWare Logic libraries enable SoC designers to optimize for power, performance, area and yield and are available to customers for the GLOBALFOUNDRIES 65LPe process through Virage Logic’s foundry sponsored IP program.