Azuro introduced version 5.2 of PowerCentric clock tree synthesis tool and version 1.4 of Rubix clock concurrent optimization tool. Clock concurrent optimization is a new approach to clock tree synthesis which builds useful skew-based clocks concurrently with performing logic gate sizing and placement. The key defining characteristic of clock concurrent optimization is that the timing picture being considered by all its underlying algorithms is a true propagated clocks view of timing based on real propagation of clock signals through the clock network.
PowerCentric is a clock tree synthesis tool for digital standard cell-based chip designs. It reduces chip power by up to 20% and reduces clock area and insertion delay by up to 30%. The product also dramatically increases productivity on designs with complex re-convergent multi-mode clock networks. PowerCentric 5.2 features a proprietary new criticality-aware clustering algorithm to further reduce clock insertion delays by an average of 15% without any impact on clock power, area or skew. The latest release also includes full support for version 1.1 of the Common Power Format (CPF). PowerCentric 5.2 is available now and is already in production use at several large sites.
Rubix is a unified placement, sizing, and useful skew-based clock tree synthesis tool for digital standard cell-based chip designs. It increases clock frequencies by up to 25%, reduces leakage power by up to 30%, and accelerates timing closure in the backend of the design flow by up to two months. Rubix 1.4 includes refinements to the tool’s underlying timing-driven placement, logic sizing, and useful skew-based clock tree synthesis algorithms, resulting in an average 15% increase in clock frequencies beyond traditional skew-balanced flows, 5% higher than the previous version of Rubix. The latest release also includes full support for version 1.1 of the Common Power Format (CPF). Rubix 1.4 is available now and is already in production use at several large sites.
More information: Azuro