The 2010 Symposia on VLSI Technology and Circuits will feature technology experts from SEMATECH. The event will take June 15-18 at the Hilton Hawaiian Village in Honolulu, Hawaii. SEMATECH will discuss the power and performance features that are critical to implementing next-generation devices, based on leading-edge research in areas such as logic and memory technologies, high-k/metal gate (HKMG) materials, and non-planar and planar CMOS technologies including exciting new high mobility channels and finFET designs.
SEMATECH VLSI Symposia Sessions
- Short course: Emerging Logic and Memory Technologies for VLSI Implementation
- High Performance Device Options: High Mobility Non-Si Channels, Prashant Majhi, program manager of FEP SEMATECH
- Emerging Disruptive Scaling Options: 3D I Interconnects / Implications, Sitaram Arkalgud, director of 3D Interconnect SEMATECH
- Enhanced Performance in SOI FinFETs with Low Series Resistance by Aluminum Implant as a Solution Beyond 22nm Node – explores an approach to scale Rext while maintaining control of short channel effects in scaled finFETs.
- SiGe CMOS on (110) Channel Orientation with Mobility Boosters: Surface Orientation, Channel Directions, and Uniaxial Strain – results obtained in this work allow the integration of high mobility SiGe CMOS on single (110) to enhance overall performance without the process complexity associated with hybrid channel approaches.
- Technology rump session: What Will End Moore’s Law? Scott Kramer, vice president of manufacturing technology at SEMATECH
- Si Tunnel Transistors with a Novel Silicided Source and 46mV/dec Swing – demonstrates a novel tunneling field effect transistor fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and high dopant density by dopant segregation.