ZeBu Hardware Assisted Verification Platforms Support TLM-2.0

Through a TLM-2.0 transactor adapter, EVE’s ZeBu fast emulation platforms now support the Transaction-Level Modeling Standard (TLM)-2.0, the Open SystemC Initiative (OSCI) interface standard for SystemC model interoperability and reuse. TLM-2.0 support gives software developers and hardware verification teams an interoperable way to map their SoC development environments to EVE’s emulators. It ties both ESL virtual platforms and simulation environments more closely to ZeBu and to each other, providing a standards-based methodology to reuse components for software development, hardware verification and hardware/software co-verification.

The TLM-2.0 transactor adapter is compatible with the OSCI TLM-2.0 standard, supporting multiple targets and initiators, blocking and non-blocking transport interfaces, and the Loosely Timed (LT), Loosely Timed Temporal Decoupled (LTD) and Approximately-Timed (AT) coding styles.

At the system level, users can integrate the TLM-2.0 transactor adapter with Electronic System Level (ESL) virtual platforms, as well as with advanced SystemVerilog hardware verification environments. At the emulator level, the ZeBu TLM-2.0 transactor adapter is an open architecture that enables interoperability with other ZeBu transactors, either from EVE’s transactor catalog or created using ZEMI-3.

TLM-2.0 support for ZeBu enables the creation of high-performance hybrid virtual platforms that combine SystemC and register transfer level (RTL) models, in a fully scalable, accurate and flexible manner, bridging the gap between software modeling and hardware implementation.

More information: EVE