Mentor Graphics is offering a webinar titled, Reducing Design Cost and Time With Concurrent DFM Verification. The webcast will take place Jun 2, 2010 from 2:00 PM to 2:45 PM (Eastern US time). The online seminar is ideal for CAD management with time and cost objectives, NPI engineers seeking to achieve first pass manufacturability, and PCB designers trying to efficiently integrate manufacturing constraints into their design process. The webinar will be presented by Patrick McGoff of Mentor Graphics.
Reducing Design Cost & Time With Concurrent DFM Verification Topics
- An improved methodology for manufacturability verification that can easily be integrated into your current flow
- The latest updates to the industry-leading solution for DFM validation
- How to reduce design cycles and improve product quality by concurrently verifying for manufacturability
Mentor Graphics Concurrent DFM Verification Webinar Overview
The hand-off between design and manufacturing is rarely seamless. Inevitably, the manufacturer finds issues that will result in increased cost or lower yield. If you’re lucky, they’ll show you the problem areas and give you a chance to fix them – this is time-consuming and error-prone, but at least keeps you in control of your design. In other cases, the manufacturer will elect to make the ‘fixes’ themselves to save time, improving manufacturability to the detriment of product performance (e.g. with high-speed multi-gigabit interconnect). Instituting a process of DFM verification concurrent to the board layout will significantly reduce the time between finding and fixing a manufacturability issue, minimize costly prototype re-spins, and result in products that perform their desired function. Mentor’s DFM verification solution plugs directly into your existing design process, integrating with your CAD system and maintaining communications and rule sets from manufacturing to optimize your design before the first prototype.
More information: Reducing Design Cost & Time With Concurrent DFM Verification