Webinar: Synthesizable Models Enable Early Emulation and Rapid Prototyping

Bluespec is offering a webinar titled, Synthesizable Models Enable Early Emulation and Rapid Prototyping. The webcast will take place Wednesday, June 2, 2010 at 11:00 AM PDT (2:00 PM EDT / 18:00 GMT). The webinar will be presented by Rishiyur S. Nikhil, co-founder and CTO of Bluespec, Inc.

In the webinar, engineers will learn how to get complex models running at MHz speeds in weeks. The webcast will explore typical modeling issues, such as the modeling gap and simulation bottleneck, and explore modeling tradeoffs between development time, execution time and accuracy. Then the online seminar will explain how synthesizable models, test benches, and transactors enable early emulation and rapid prototyping (illustrated by a demo of synthesizable models running at 10s of MHz on an FPGA board).

Bluespec Synthesizable Models Webinar Overview

Emulation and rapid prototyping typically cannot begin until late in a project, when well-verified RTL is available. This can severely delay software development, performance validation and verification. With synthesizable models, test benches and transactors, emulation and rapid prototyping can be leveraged much earlier in the development cycle, well before new RTL blocks are ready. And, synthesizable models can fix the simulation bottlenecks inherent in C/C++/SystemC models by running at 10s of MHz in emulators, even with hardware-accuracy. Synthesizable modeling provides the only solution that closes the gap between models and RTL implementations. Bluespec synthesizable models interoperate with RTL, can be incrementally and selectively refined to a full implementation, and allow high-speed emulation at all stages of development.

More information: Synthesizable Models Enable Early Emulation & Rapid Prototyping