Titan Analog Layout Accelerator and Titan Analog Virtual Prototyper

Magma Design Automation introduced the Titan Analog Layout Accelerator (ALX) and the Titan Analog Virtual Prototyper (AVP). Titan ALX and Titan AVP accelerate the creation and optimization of new analog design layouts, and automate the reuse of existing analog layouts in new processes and technologies. Titan ALX automatically migrates an existing analog layout to a new target technology without any DRC violations while preserving analog design intent. Titan AVP creates fast and accurate device-level prototypes and captures layout-dependent proximity effects early in the circuit design phase. Titan ALX and Titan AVP will be in production release in June 2010.

Titan Analog Virtual Prototyper (AVP) -

Titan Analog Virtual Prototyper (AVP) Features

  • Hierarchical layout generation with flattening capabilities based on real PDK
  • Prototype placement mirrors placement in schematic initialization
  • Quick manual placement – PowerPoint style grouping ungrouping of objects
  • Simplifies entry of placement constraints including symmetry, alignment and spacing
  • Support for device modules
  • Ability to add guard rings on groups
  • Interactive placement and creation of a generic floorplan
  • Hierarchical cross-probing between schematic and layout
  • Virtuoso data compatibility using translators
  • Works on Titan LE instances and supports PCells/Pycells
  • Fast and high-capacity congestion-aware global/detail placement
  • Flexible and rich placement constraints
  • Intuitive and easy-to-use constraint manager
  • Rule-driven automatic placement (automatic device chaining, device row planning, dynamic device abutment during placement)
  • Interactive placement
  • Auto-stack rule extraction – supports hierarchical stack rules
  • Hierarchical update of layout/floorplan based on changes in schematic
  • Complete control on hierarchy during update
  • Maintains relative placement, symmetry, alignment and spacing
  • Extraction of proximity parameters from partial layout
  • Netlisting of extracted parameters from the prototype layout
  • Complete reuse of schematic testbench for layout-aware simulation
  • Back annotation of extracted proximity parameters onto schematic
  • Parasitic net cap estimation based on placement
  • Relative placement constraints written for circuit sizing
  • Automatic update of placement with the optimized circuit sizes
  • Net route equations for parasitic cap estimation during optimization
  • Supported platforms: Linux 32 and 64 bit

Titan Analog Layout Accelerator (ALX) Features

  • Migrate analog circuit layout while preserving layout beauty and design intent
  • Support complex DRC/DFM rules in the most advanced nodes, including poly spacers, discrete poly rules, max-device width, conditional/corner spacing
  • Automatic hierarchy preservation
  • Automatic PCell creation using target node PDK
  • Automatic preservation of symmetry and alignment
  • Automatic or custom device sizing, including custom support for transistor folding / fingering options
  • Schematic-driven device sizing
  • Automatic device type changes, such as n+ resistor to OD resistor
  • Designer toolbox for helping custom layout engineer during new design implementation or modifying existing layout due to ECOs
  • Automatic DRC clean-up for a quick and dirty layout; go from dirty layout to DRC-clean layout, instantly
  • Quick design prototyping by migrating all critical design layers: well, diffusion, poly, vias and metals
  • Automatic handling of pin/pitch matching constraints – quick DRC vs. area tradeoff studies
  • Flexible handling of difficult hierarchy constraints: unimportant aspects of hierarchical layouts are smartly relaxed to reduce DRC errors by orders of magnitude
  • Flexible handling of PCell constraints: automatically computes non-default values for the layout parameters of each PCell to significantly reduce DRC errors
  • Abstract and easy to tweak rule deck to calibrate layout
  • Speed up circuit and layout effort by quick what-if experiments changing layout rules

More information: Magma Design Automation