Real Intent Ascent Lint v1.3

Real Intent rolled out version 1.3 of Ascent Lint. The new version adds VHDL checks to its existing Verilog checks. It is a tool that performs syntax and semantic Hardware Description Language (HDL) lint checks for complex SoC designs. Ascent Lint features a fast engine and low noise report for debugging electronic designs. Ascent Lint 1.3 is available now.

Real Intent Ascent Lint tool

Ascent Lint 1.3 Features

  • Ambiguous modeling
  • Differences between simulation and synthesis semantics
  • Naming and RTL coding conventions
  • VHDL subset restrictions to enforce modeling clarity and reduce unnecessary complexity
  • Operations with hidden or expensive implementation costs
  • Downstream tool flow issues
  • Network and connectivity checks for clocks, resets, and tristate-driven signals
  • Testability

More information: Real Intent Ascent Lint (pdf)