SynaptiCAD EDA Tool Suite, Version 15

SynaptiCAD EDA Tool Suite, version 15, features new versions of WaveViewer, Timing Diagrammer, WaveFormer, DataSheet, VeriLogger Extreme, BugHunter, TestBencher Pro and V2V. SynaptiCAD EDA Tool Suite v15 also includes improvements to the Gates-On-The-Fly Netlist Editor.

SynaptiCAD EDA Tool Suite v15 New Features

All Waveform Viewers and Editors

  • Tooltip displays next/previous state of bus segments in timing diagram window (disable via View menu)
  • Show partial extended state when segment is too small to show entire state in diagram window
  • Markers labels “float” at top of timing diagram window when not attached to a signal
  • Hover over a Group Bus name to display member signals of the bus in a tooltip
  • Japanese font compatibility
  • User-defined radixes can be stored in filter files

All Waveform and Timing Diagram Editors

  • Python-based Waveform block equations
  • Special View menu mode for rapid editing of Waveform block equations
  • Timing diagram Autosave/recovery in case of system failure
  • Delay correlation info added to the exportable timing analysis report
  • Mass event edits using 1 and 2 keys to drag edges are three orders of magnitude faster
  • Modified TIM file import to read TIM files that have been manually edited via a text editor
  • New icons to indicate signals are “compare” signals
  • Improved HTML-based help for UNIX

WaveFormer Pro/DataSheet Pro/TestBencher only

  • Import of Tektronix Mixed-Signal Oscilloscope waveforms (MSO 2000,3000, and 4000)
  • Integration with TI’s SystemC-based High-end Timer simulator

BugHunter HDL Debugging GUI (included in VeriLogger and TestBencher)

  • Double click in the new scope column of a Show Driver window navigates to the scope instance
  • Change driver signal values from a Show Driver window
  • Watched signals add after the last selected signal (same behavior as when pressing “Add Signal” button)
  • Open Gates-on-the-Fly schematic windows from components in BugHunter’s hierarchy window to analyze gate-level designs

VeriLogger Extreme Simulation Engine

  • 64bit windows simulation support (requires download of free Windows SDK 7 from Microsoft)
  • Support for Xilinx SecureIP models
  • Faster simulation runtimes with cycle-based and non-blocking assignment optimizations (8x faster on opencores ac97 benchmark)
  • Faster simulation of timing checks
  • Reduced memory usage by over 4x for large designs
  • Improved code generation for smaller simulator executables and faster compile times
  • Faster dependency checking on simulation rebuilds
  • Enhanced PLI 1.0 and 2.0 support (all VPI/ACC functions now supported except put_delays/attribute functions)
  • Support -g/-G/+defparam options to override parameter values from the commandline
  • Internally tested against Actel and Altera IP Cores

V2V Verilog/VHDL Translator

  • No_Component_Check is now on by default when translators are executed from BugHunter GUI
  • VHDL2Verilog supports constants defined as records
  • Many bug fixes

Gates-On-The-Fly Verilog Netlist Editor

  • 64-bit Linux support
  • New read_file api can import static timing analyzer data
  • New fix_setup and fix_hold API calls for automatically fixing setup and hold violations detected by static timing analyzers
  • Added replace_logic_cone API function to enable more powerful ECO operations
  • Added write_cdn API function to write out ECO results in Cadence SOC Encounter script format

3rd Party API enhancements (control waveform viewers/editors via 3rd party tools)

  • New API functions for controlling signal and marker color, setting marker type, and get and set of tooltip display
  • Python-based interface for reading/writing binary timing diagram files (btim) — requires optional license
  • New syncadlauncher dll allows 3rd party application to perform basic control of syncad.exe without including a CORBA ORB

More information: SynaptiCAD Tool Suite