Magma Design Automation introduced SiliconSmart ACE Memory Characterization. It features the FineSim Pro simulation technology, dynamic circuit reduction through smart netlist pruning, automatic internal node identification, constraint acceleration, and template-guided function descriptions for vector generation. With SiliconSmart ACE Memory Characterization, integrated circuit (IC) designers can reduce turnaround time and deliver better results for designs targeted at 28-nanometer (nm) and smaller process nodes. SiliconSmart ACE Memory Characterization is an extension to SiliconSmart ACE and is available now.
SiliconSmart ACE Memory Characterization Overview
FineSim Pro simulation technology blends both SPICE simulation and Fast-SPICE simulation into one single circuit simulator. SiliconSmart ACE Memory Characterization takes advantage of its “multi-mode” engine to make appropriate tradeoffs for accuracy and speed. For example, it assigns SPICE simulation to analog circuitry such as sense amps to ensure accuracy, and assigns Fast-SPICE simulation to digital circuitry such as control logic for speed. FineSim Pro’s industry-leading technology for analyzing non-ideal power rails for memory circuits greatly increases overall simulation speed by intelligently partitioning the power rail RC network, signal RCs and MOS transistors.
Stimuli or vectors to excise a memory circuit for a specific measurement in characterization usually propagate through a specific portion of the circuit. To increase throughput, a memory characterization tool must have the capability to remove the inactive portions of the circuit from the simulation deck. Unlike the traditional simple-but-inaccurate path-based reduction methodology, SiliconSmart ACE memory characterization employs a smart netlist-pruning algorithm that utilizes FineSim Pro simulation for circuit structural analysis that identifies and eliminates non-essential active devices and RCs. The actual simulation deck after this highly efficient dynamic circuit reduction per measurement vector set is much smaller than the original netlist, shortening simulation runtime.
Constraint measurements such as setup and hold in memory characterization are not only very time-consuming, but also difficult to probe. This is because the data and clock usually meet at an internal node, which is hard to locate in a fully RC-extracted netlist. SiliconSmart ACE Memory Characterization runs the FineSim Pro simulation to monitor toggling behaviors of potential candidates and, after a thorough heuristic analysis, automatically identifies the right internal node for constraint measurement. In addition to the constraint acceleration technology included in SiliconSmart ACE for standard cells, SiliconSmart ACE Memory Characterization includes memory constraint acceleration technology that selectively saves memory states and then intelligently reuses these states to improve runtime over the multiple clock cycle iteration process without any loss of accuracy.
Like SiliconSmart ACE, which provides ease of use through automatic function recognition for standard cell characterization, SiliconSmart ACE Memory Characterization reduces the burden of setup by providing a template library to describe various memory functions. This high-level functional description automatically creates all control files and all the necessary simulation vectors for all the arcs for a re-characterization of a memory instance with the same model structure but more accurate numbers through simulation.
More info: Magma Design Automation