Evatronix 65C02 Microprocessor IP Core

The Evatronix C65C02 IP core is a 65C02 compatible microprocessor IP core that complies with the original 6502 Instruction Set Architecture by MOS Technology. The C65C02 is a fast 8-bit microprocessor IP that implements the same instruction set as the 65C02 microprocessor chip, which is an upgraded version of the NMOS-based MOS Technology 6502 8-bit CPU. The Evatronix C65C02 IP core is available for licensing now. The core includes synthesis and simulation support scripts for most environments, Verilog or VHDL test bench, and a reference design for the proprietary evaluation board.

Evatronix C65C02 Microprocessor IP Core

  • 65C02 compliant
  • Control Unit with both maskable and non-maskable interrupts
  • Decreased overall interrupt latency
  • Synchronization with external events
  • Sixteen addressing modes — including indirect index and zero page
  • 8-bit arithmetic-logic unit can operate on signed and unsigned binary numbers as well as binary-coded decimal numbers
  • 8-bit Instruction Decoder with 69 instructions and 212 opcodes
  • 8-bit ALU for decimal and binary arithmetic as well as logical/logical shift operations
  • External Memory interface addressing up to 64KB
  • Two instructions for power management – STP for processor halt and WAI for wait for interrupt

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