eASIC eTools 8.1 Design Suite for 45nm Nextreme-2 Designs

eASIC rolled out eTools 8.1 Design Suite for 45nm Nextreme-2 designs. The eTools 8.1 based design flow helps designers to simply perform front-end design conversion and back-end implementation. New features and enhancements in eTools 8.1 enable designers to reduce overall design time by up to 40% while increasing design performance by up to 30% compared to the previous eTools 8.0 suite. FPGA and ASIC designers can try a 30-day evaluation of eTools 8.1 for free.

eASIC eTools 8.1 Design Suite for 45nm Nextreme-2 designs

eTools 8.1 operates in collaboration with logic synthesis software from Magma DA or Synopsys. After synthesis, designers use the eTools 8.1 ePlanner to map the I/O pins, and floorplan the timing critical portions of their design if required. The placement stage is divided into a global and detailed placement step. Global placement works on a coursing granularity of logic fabric detail and with the incremental placement enables fast turns of the design implementation to help designers find the optimal placement and fan out control quickly. The final detailed placer completes the placement stage giving accurate timing estimate and analysis through the parallax timing engine.

eTools 8.1 Highlights

  • Improved Push-button GUI-based tools to help FPGA designers come rapidly up to speed
  • Timing constraints conversion and Auto Memory replacement utilities facilitate faster design conversion from FPGA designs
  • Increased IP support in eZ-IP Wizard including:
    • FIFO (synchronous and asynchronous)
    • PLL
    • DDR-2 PHY
    • LVDS SERDES
  • Interactive Regioning enables hierarchical layout of timing critical portions of design to accelerate timing closure
  • Availability of complete placement tool (ePlacer) enabling a placed-gates netlist hand-off and greater design control over the design flow
  • Multi-Processor core support for 3x faster placement tools
  • Improved Quality of Results through improved placement and physical re-synthesis algorithms
  • Hierarchical Design Flow allows implementation on large designs to be distributed across numerous team members accelerating to be distributed
  • IP Macro Design Flow allows 3rd party IP vendors or designers to close timing on IP blocks and capture that layout information into the eZ-IP Wizard for distribution of the IP
  • Interactive Placement viewer for timing analysis of design including congestion analysis, fly line / worst case path examination and fine grain placement adjustment
  • Physical Re-Synthesis to control net fan-out and fine-grain optimize of the design netlist in order to improve overall timing performance on critical paths

More info: eASIC