Tensilica ConnX 545CK 8-MAC VLIW Digital Signal Processor Core

Tensilica announced Revision C of the ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core for system-on-chip (SOC) designs. In 65GP optimized for high speed, the ConnX 545CK delivers over 600 MHz operation. The third generation dataplane processor (DPU) core deliver up to 20% faster clock speed, 11% smaller die and up to 30% lower power consumption. The ConnX 545CK Revision C is available now.

Tensilica ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core

ConnX 545CK DSP Core Overview

  • High performance and efficiency for DSP operations
  • 3-issue VLIW DSP with 8-way SIMD units
  • Compiler automatically vectorizes code
  • DSP instructions native to single core, modeless switching between 16-, 24- and 64-bit instructions
  • Dual 128-bit load/store units
  • Eight 16-bit MACs that operate in SIMD mode
  • 32-bit input/output Queue (FIFO-like) interfaces
  • Viterbi convolutional coder accelerator
  • AHB-lite and AXI bridges
  • High and flexible computational performance
  • Performance headroom allows operation at lower frequency to reduce power consumption
  • Single core, single development environment due to native DSP instructions
  • Ideal for communication baseband applications
  • High I/O throughput; higher than XY DSPs
  • Bypass system bus and communicate directly via Queue interfaces
  • Drop into existing AMBA-based systems

More info: Tensilica